SHA-224/256复用IP核的设计与实现

The design and implementation of the multiplexing SHA-224/256 IP cores

摘要: 以SHA-224与SHA-256算法的相似性为基础,设计了一个可时分复用的SHA-224/256IP核.该设计采用并行结构与流水线技术,在简化硬件设计的同时,提高了该IP核的运行速度(速度提高26%).最终以Altera的EP2C20F484C6芯片为下载目标,其时序仿真可正常运行在100MHz的时钟频率下,该IP核可广泛应用于信息安全领域.

Abstract: In this paper,we designed a time-division multiplexing SHA-224/256 IPcore based on the algorithm's similarity.The IPcore used parallel structure and pipeline technology to simplify the hardware designing and improved the speed of the IPcore.Finally we implemented the IPcore in Altera's EP2C20F484C6 FPGA.We also gave the result of timing simulation which demonstrates the IPcore can run under the 100MHz frequency.This IPcore could be widely used for digital signature system and double-key system of 3DES.