Abstract:
Aiming at the problem that the throughput between the card board and the host system is too small in the process of data transmission, the system processor speed is slow, and a high-performance Direct Memory Access (DMA) engine architecture design scheme is proposed. First, a DMA single-core engine architecture is proposed for the improved distributed aggregation DMA transmission mode. Then, based on the DMA single-core engine architecture compatible with Xilinx Field Programmable Gate Array (FPGA) 6 and 7 series, it is proposed that two Peripheral Component Interconnect Express (PCIE) IP cores communicate with PCIE through x8 channels. The dual-core DMA engine design scheme used by the bridge in parallel. Finally, the Xilinx PCIE Gen2 is used to test the performance of the DMA engine with the Virtex-6 FPGA development board. After testing, the throughput of the DMA single-core engine can reach up to 3 721 MB/s, at the same time, the dual-core engine can reach 6 925 MB/s, which is about twice that of the single-core engine, meeting the design requirements. This design has good stability and can be widely used in high-speed data acquisition systems such as satellite telemetry, Unmanned Aerial Vehicle intrusion data acquisition and radar systems.