Abstract: In this paper,we designed a FFT butterfly computing unit based on the pipeline structure of CORDIC algorithm,and finally realized a two-dimensional FFT processor supported high sample which used the ranks of decomposition algorithm based on FPGA.Its design had used VHDL hardware description language and used the Quartus Ⅱ 8.0 to synthesize,wire and download test validation to the DE2 experiment platform.The processing reduced the consumption of storage for the high number of sample capacity of the FPGA chips.It had good reconstruction,simple hardware structure,high safety,quick speed and could be widely used in digital signal processing field.