Abstract: To meet the requirements for real-time and security of high-speed network transmission in the current,we designed a kind of AES encryption/decryption IP core based on AES-128/192/256 algorithm and using pipeline reconfigurable structure in this paper.Meanwhile,this IP core,the Nios Ⅱ processor,the network controller,including other function modules and the corresponding peripherals are integrated by SOPC technology,implementing a network adapter on chip can according to specific application resources and safety demand to configuration flexible.The design uses hardware description language VHDL,and layout and wire on QuartusⅡ8.0.Finally the system is downloaded to DE2 for testing.The design hardware structure is simple,security,high-speed,flexibility,which can be widely used in the field of network information security.